Hays (Schweiz) AG
Lausanne
Meine Aufgaben You will define the block-level specifications of high-speed digital circuits You will cooperate with analog/mixed-signal designers. You will be in charge of the RTL design and the testing. You will work closely with verification and physical implementation engineers You will support the post-silicon lab for the bring-up, debug, ch
Stellenquelle: Hays (Schweiz) AGu-blox AG
Etoy, Waadt, Switzerland
Great vacancy Senior Physical Design Engineer hiring now Great vacancy Senior Physical Design Engineer hiring now Data Privacy u-blox respects your privacy and is committed to protecting your personal information that you share with us. Your information will not be disclosed to any unauthorized third party, i.e. u-blox will only disclose your info
Stellenquelle: u-blox AGu-blox AG
Etoy, Waadt, Switzerland
Great vacancy Senior Physical Design Engineer hiring now Great vacancy Senior Physical Design Engineer hiring now Data Privacy u-blox respects your privacy and is committed to protecting your personal information that you share with us. Your information will not be disclosed to any unauthorized third party, i.e. u-blox will only disclose your info
Stellenquelle: u-blox AGMicrotech Global Limited
, Vaud
Role: Principal Design Engineer Location: Switzerland About the role: You must have demonstrated success in digital design & verification/infrastructure development for digital FPGAs/ASICs. Other key skills include technical/project leadership, documentation, RTL design knowledge, and backend flow and tools knowledge. The position requires both tec
Stellenquelle: Microtech Global LimitedmicroTECH Global Limited
, Vaud, Switzerland
Role: Principal Design Engineer Location: Switzerland About the role: You must have demonstrated success in digital design & verification/infrastructure development for digital FPGAs/ASICs. Other key skills include technical/project leadership, documentation, RTL design knowledge, and backend flow and tools knowledge. The position requires both
Stellenquelle: microTECH Global LimitedmicroTECH Global Limited
, Vaud, Switzerland
Role: Principal Design Engineer Location: Switzerland About the role: You must have demonstrated success in digital design & verification/infrastructure development for digital FPGAs/ASICs. Other key skills include technical/project leadership, documentation, RTL design knowledge, and backend flow and tools knowledge. The position requires both
Stellenquelle: microTECH Global LimitedFastree3D SA
Lausanne, Waadt, Switzerland
Senior Analog IC Design Engineer Reports to: CTO + Locally to Managing Director SUMMARY Seeking a professional IC Design Engineer proficient with IC design and photonics to drive the design and characterization of the next generation of 3D imagers for mobile vision applications in robotics and automotive. Successful applicants will be part of a sk
Stellenquelle: Fastree3D SAFastree3d Sa
Lausanne, Waadt
Senior Analog IC Design Engineer Reports to: CTO + Locally to Managing Director SUMMARY Seeking a professional IC Design Engineer proficient with IC design and photonics to drive the design and characterization of the next generation of 3 D imagers for mobile vision applications in robotics and automotive. Successful applicants will be part of a sk
Stellenquelle: Fastree3d SaLausanne, Waadt, Switzerland
CHF 80.000 - 100.000
Working for a cutting edge semiconductor company, I have a brand-new Senior Digital Design Verification opportunity to work on the latest high-speed communication ASIC technologies.
You will be part of key R&D projects for complex IP - working closely with designers, architects and other verification engineers in the wider business.
110-120k CHF
Must have skills:
University degree - BSc / MSc / PhD in Electronics, Microelectronics, Physics or Computer Science
Industry experience in digital verification - for FPGA / ASIC (VHDL and / or Verilog, System verilog)
Good language & communication skills in English
UVM environments, libraries and complex test-benches for digital IPs
Working for a cutting edge semiconductor company, I have a brand-new Senior Digital Design Verification opportunity to work on the latest high-speed communication ASIC technologies.
You will be part of key R&D projects for complex IP - working closely with designers, architects and other verification engineers in the wider business.
110-120k CHF
Must have skills:
University degree - BSc / MSc / PhD in Electronics, Microelectronics, Physics or Computer Science
Industry experience in digital verification - for FPGA / ASIC (VHDL and / or Verilog, System verilog)
Good language & communication skills in English
Strong coding skills - python / C / C++ / System C
UVM environments, libraries and complex test-benches for digital IPs
Bonus / "nice-to-have" skills:
Definition of complex digital architecture
High-speed digital connectivity and protocols - Serdes, ethernet, USB, PCIe, AMBA / AXI, MAC, PHY, cache coherency - MESI
Testing / validation
Matlab / Simulink modelling experience
confident software coding skills - C++ / python etc
formal / software verification - jasper gold, onespin, SVA - system verilog assertions
language & communication skills in French
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